1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a fuse element that allows information to be stored in a non-volatile manner.
2. Description of the Background Art
For example, a semiconductor memory device having memory cells arranged in an array form in row and column directions include a plurality of extra memory cell rows and memory cell columns. A system for improving the yield of chips on a wafer has been conventionally adopted in which deficient memory cells, memory cell rows, or memory cell columns caused by defects are replaced with the extra memory cell rows or memory cell columns for relief.
This system requires an internal circuit in which poor addresses sensed by a wafer test are stored in advance in a non-volatile manner in the chip, and the row and column addresses input at the time of use are monitored at all times and, when an input of poor addresses is sensed, they are replaced with the extra lines.
As the aforesaid internal circuit, an address sensing circuit is widely used which cuts a polysilicon wiring, an aluminum wiring, or the like with a laser beam, as disclosed, for example, in the document xe2x80x9cIEEE Journal of Solid-State Circuits Vol. SC-18No. 5, October 1983, pp. 441-446xe2x80x9d.
FIG. 32 is a circuit diagram illustrating a construction of a conventional address sensing circuit 500.
Referring to FIG. 32, an address sensing circuit 500 includes fuse elements 502.0 to 502.n each one end of which is connected to a node N500, and N-channel MOS transistors 504.0 to 504.n whose drains are connected respectively to the other ends of the fuse elements 502.0 to 502.n, whose gates receive addresses ADD less than 0 greater than  to ADD less than n greater than , and whose sources are all connected to the ground voltage.
The address sensing circuit 500 further includes P-channel MOS transistors 506, 508 connected in parallel between a node to which the power source voltage Vcc is given and the node N500, and an inverter 510 whose input is connected to the node N500 and which outputs a sensing signal MIS.
A precharging signal PG is given to the gate of the P-channel MOS transistor 506. The gate of the P-channel MOS transistor 508 receives the sensing signal MIS.
An address of positive logic and a complementary address, which is an inverted address thereof, are input via a fuse to a decoder of an extra column of the semiconductor memory device (hereafter referred to as an extra decoder). By cutting off the fuse corresponding to the address of a poor memory cell with a laser beam, the address of the poor memory cell is stored in a non-volatile manner.
On the other hand, the address sensing circuit 500 functions in such a manner that, when the input address coincides with the address corresponding to the poor memory cell stored in a non-volatile manner, a sensing signal MIS for inactivating the normal decoder connected to the poor column is output to replace the poor column with an extra column.
Here, an example has been given for a case in which a column is replaced; however, a similar construction is adopted in the case of replacing a poor row with an extra row.
Further, a fuse element is used also for tuning analog circuits and others whose characteristics change chip by chip. In this case also, the yield can be improved by tuning chip by chip.
The conventional fuse element requires an expensive laser cutter for cutting, and has a problem of poor precision in cutting the fuses. In order to solve these problems, an antifuse element is used in recent years. For example, U.S. Pat. No. 5,631,862 and 2000 IEEE International Solid-State Circuits Conference xe2x80x9cWP 24.8 Antifuse EPROM Circuit for Field Programmable DRAMxe2x80x9d disclose a circuit example that uses an antifuse element. The circuit disclosed in the latter document will be described hereafter.
FIG. 33 is a circuit diagram illustrating a construction of an antifuse program circuit 520.
Referring to FIG. 33, an antifuse 526 receives a voltage Vpgm at one end thereof and the other end thereof is connected to a node N502. The antifuse 526 in its original state is in a non-conducted state between the two electrodes thereof. When a dielectric substance between the two electrodes is destroyed by allowing the voltage Vpgm to be a high voltage, an electrically conductive type path having a resistance value of about several K xcexa9 is formed between the two electrodes of the antifuse 526.
In a normal operation mode, the voltage Vpgm is maintained at the power source voltage Vcc; however, in changing the antifuse 526 into a conducted state between the two electrodes (hereafter referred to as blowing), a high voltage is applied as the voltage Vpgm.
The signal SA is a signal for selecting whether the antifuse 526 is to be blown or not. In carrying out a reading operation, when the signal SNL is activated after the precharging signal PG is once activated to a L(low)-level to set the voltage of the node N501 to the power source voltage Vcc, it is possible to read whether the antifuse 526 has been blown or not. The read data are latched by the latch circuit constructed with the inverters 544, 546.
FIG. 34 is an operation waveform diagram for describing a fuse blowing operation of the antifuse program circuit 520 shown in FIG. 33.
Referring to FIG. 34, the signal PG is activated to the L-level at the time t1 to initialize the voltage of the node N501.
Subsequently, the signal SA is set at a H(high)-level at the time t2 to fix the voltage of the node N501 at the L-level. Thereafter, the voltage Vpgm is set at a voltage VBP such that the antifuse 526 undergoes dielectric breakdown. Then, the antifuse 526 is blown.
FIG. 35 is an operation waveform diagram for describing an operation in the case where the fuse-blowing is not carried out.
Referring to FIG. 35, the signal PG is activated to the L-level at the time t1 to t2 to initialize the voltage of the node N501.
Next, the signal SA is maintained at the L-level without change at the time t2. This point is different from the case of FIG. 34 in which the signal SA is activated to the H-level to carry out the fuse-blowing.
At the time t2, a high voltage is applied as the voltage Vpgm. However, the node N501 is in a so-called floating state, and its level is at the H-level. Since the power source voltage Vcc is given to the gate of the N-channel MOS transistor 528, the voltage difference Vgs between the gate and the source of the N-channel MOS transistor 528 is 0V, so that the N-channel MOS transistor 528 is in a non-conducted state. Therefore, the node N502 is in a floating state, so that even if a high voltage is applied as the voltage Vpgm, the voltage of the node N502 rises by capacitive coupling to become approximately the same voltage as the voltage Vpgm. For this reason, the voltage applied between the two electrodes of the antifuse 526 is a voltage V5 of FIG. 35 which is approximately near 0V, so that the antifuse 526 is not blown.
As described above, by performing the operations shown in FIGS. 34 and 35 for the antifuse corresponding to each address, the address can be programmed.
Next, the reading operation will be described.
FIG. 36 is an operation waveform diagram for describing a reading operation of the antifuse program circuit 520.
Referring to FIGS. 33 and 36, the voltage Vpgm is set at the power source voltage Vcc as an initial state, and the signal SA is set at the L-level.
Subsequently, at the time t1, the node N501 is initialized by the signal PG.
At the time t2, the signal PG is inactivated to the H-level, and the node N501 is brought to the H-level which is a floating state.
Subsequently, at the time t3, the signal SNL is set at the H-level. Then, if the antifuse 526 has not been blown, the voltage of the node N501 is brought to the L-level by electric conduction of the N-channel MOS transistor 530.
Thereafter, at the time t4, when the signal SNL is brought to the L-level, the voltage of the node N504 is latched by the latch circuit constructed with the inverters 544, 546. By observing a signal F output from the latch circuit, the input address can be compared with the address programmed in the fuse element.
Next, in the case where the fuse has been blown, the voltage of the node N501 is not brought to the L-level even if the signal SNL is brought to the H-level at the time t3 of FIG. 36. Here, the voltage of the node N501 is determined by the ratio of the resistance value of the N-channel MOS transistor 530 in a conducted state, the resistance value of the antifuse 526 after being blown, and the resistance value of the P-channel MOS transistor 528. If the resistance value of the N-channel MOS transistor 530 in a conducted state is set at a sufficiently high level, the voltage of the node N501 can be maintained in a H-level state.
Then, when the signal SNL is brought to the L-level at the time t4, the voltage of the node N501 is brought to the H-level, and is latched by the latch circuit that outputs the signal F. The latch data are used as an input address judging signal in the same manner as in the case where the fuse-blowing has not been carried out.
However, in the conventional antifuse circuit 520, when the antifuse 526 undergoes dielectric breakdown after the time t2 of FIG. 34, the electric current continues to flow, even thereafter, to the ground node via the antifuse 526 and the transistors 528, 530 from the node to which the voltage Vpgm that has become a high voltage is given. It may happen that, by this electric current, the voltage Vpgm falls. In the case where a number of antifuses are to be blown at the same time, decrease in the voltage Vpgm may possibly make it difficult to blow another antifuse after one antifuse is blown.
Furthermore, if there exists an antifuse 526 that has not been completely blown, its resistance value may possibly become larger than the resistance value of the N-channel MOS transistor 530 to pull the voltage of the node N501 to the L-level side thereby to cause erroneous reading operation.
An object of the present invention is to provide a semiconductor device including an antifuse program circuit in which an antifuse can be cut off with certainty, the address of a poor memory cell can be stably programmed, and a stable reading operation can be realized.
In summary, this invention is a semiconductor device including an antifuse, an electric current limiting circuit, a latch circuit, and an initializing circuit.
One end and the other end of the antifuse are connected respectively to a first node and a second node, and an electrically conductive path is formed between the one end and the other end by application of a voltage exceeding a predetermined value between the one end and the other end. The electric current limiting circuit limits an electric current flowing between the second node and a third node in accordance with a voltage of the third node. The latch circuit is for maintaining the voltage of the third node. The initializing circuit gives an initial voltage to the voltage of the third node.
According to another aspect of the present invention, a semiconductor device includes a plurality of antifuse program circuits, a gate circuit, a first pad, and a second pad.
Each of the antifuse program circuits includes an antifuse whose one end and other end are connected respectively to a first node and a second node, where an electrically conductive path is formed between the one end and the other end by application of a voltage exceeding a predetermined value between the one end and the other end; an electric current limiting circuit that limits an electric current flowing between the second node and a third node in accordance with a voltage of the third node; a latch circuit that maintains the voltage of the third node and outputs an output signal in accordance with the voltage of the third node; and an initializing circuit that gives an initial voltage to the voltage of the third node.
The gate circuit receives outputs of the plurality of antifuse program circuits. From the first pad, a blowing voltage is given to the one end from outside. To the second pad, an output of the gate circuit is given and observed from outside.
According to still another aspect of the present invention, a semiconductor device includes an antifuse.
In the antifuse, an electrically conductive path is formed between one end and other end thereof by application of a voltage exceeding a predetermined value between the one end and the other end. The antifuse includes a well region of first conductivity type that is electrically connected to the one end and formed in a semiconductor substrate; first and second impurity regions that are electrically connected to the one end and formed in an inside of the well region; an insulator film formed above a region between the first impurity region and the second impurity region; and an electrically conductive electrode layer that is electrically connected to the other end and formed above the insulator film.
Therefore, a principal advantage of the present invention lies in that, since the electric current does not flow when the antifuse is blown, the blowing voltage can be prevented from falling, thereby improving the reliability of the blowing operation.
Another advantage of the present invention lies in that, since the completion of blowing can be observed from outside, the antifuse can be blown with certainty.
Still another advantage of the present invention lies in that, since a MOS structure is used as an antifuse, the dielectric breakdown of the antifuse is facilitated.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.